1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process for depositing dielectric layers on a substrate and the structures formed by the dielectric layer.
2. Background of the Invention
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's fabrication plants are routinely producing devices having 0.13 μm and even 0.1 μm feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and to use insulators having low dielectric constants (k<4.0) to reduce the capacitive coupling between adjacent metal lines. One such low k material is spin-on glass, such as un-doped silicon glass (USG) or fluorine-doped silicon glass (FSG), which can be deposited as a gap fill layer in a semiconductor manufacturing process. Other examples of low k materials include silicon dioxide and polytetrafluoroethylene which are all commercially available. However, the continued reduction in device geometries has generated a demand for films having even lower k values.
Rose et al. (U.S. Pat. No. 6,068,884) discloses a method of depositing an insulator wherein a cyclic organosilicon compound, octamethylcylcotetrasiloxane (OMCTS), is partially fragmented to form both cyclic and chain structures in the deposited film. However, partially fragmenting cyclic precursors is difficult to control. Therefore, there is a need for a controllable process for making low dielectric constant materials that would improve the speed and efficiency of devices on integrated circuits.